The Efficient On-Chip Bus Architecture for High-Performance SoC Design
نویسندگان
چکیده
منابع مشابه
High performance asynchronous bus for SoC
It is difficult to use synchronous buses in a system-on-a-chip design due to the increase of wire delay caused by the crosstalk effect and the dificulty of the synchronization caused by the clock-skew problem. The use of an asynchronous bus is an alternative solution for the SoC design method. In this paper, we propose a new high performance asynchronous bus using a rehim-to-zero data encoding ...
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ژورنال
عنوان ژورنال: International Journal of Control and Automation
سال: 2017
ISSN: 2005-4297,2005-4297
DOI: 10.14257/ijca.2017.10.1.02